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Reduced instruction set computer
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131	25 YEARS AGO: THE FIRST ASYNCHRONOUS MICROPROCESSOR Alain J. Martin Department of Computer Science California Institute of Technology Pasadena, CA 91125, USA Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2014-01-28 17:16:01 Computer hardware Central processing unit Telecommunications engineering Quasi Delay Insensitive Microprocessors Asynchronous circuit CPU design Datapath Reduced instruction set computing Electronic engineering Electrical circuits Electrical engineering
132	Document: Proposed Rule, Register Page Number: 26 IR 1201 Source: January 1, 2003, Indiana Register, Volume 26, Number 4 Disclaimer: This document was created from the files used to produce the official CD-ROM Indiana Re Add to Reading List Source URL: www.in.gov Language: English - Date: 2007-03-16 15:54:48 Computer law Internet access Reduced instruction set computing Public comment Resource Conservation and Recovery Act Notice of proposed rulemaking Online Protection and Enforcement of Digital Trade Act Politics of the United States United States administrative law Government Law
133	PRESS RELEASE September 12, 2012 European project aims at providing innovative solutions allowing reliable circuits to be designed from low-powered unreliable components Add to Reading List Source URL: www.elfak.ni.ac.rs Language: English - Date: 2013-05-09 07:24:33 Framework Programmes for Research and Technological Development NeXT Electronic engineering Computing Engineering Apple Inc. Computer engineering Reduced instruction set computing
134	Document: Proposed Rule, Register Page Number: 26 IR 1201 Source: January 1, 2003, Indiana Register, Volume 26, Number 4 Disclaimer: This document was created from the files used to produce the official CD-ROM Indiana Re Add to Reading List Source URL: www.in.gov Language: English - Date: 2007-03-16 15:54:48 Computer law Internet access Reduced instruction set computing Public comment Resource Conservation and Recovery Act Notice of proposed rulemaking Online Protection and Enforcement of Digital Trade Act Politics of the United States United States administrative law Government Law
135	Microsoft Word - 24KE SPF05 paper current.doc Add to Reading List Source URL: www.imgtec.com Language: English - Date: 2013-10-01 09:04:24 Digital signal processing Instruction set architectures Microprocessors Parallel computing Digital signal processor MIPS architecture Multi-core processor Reduced instruction set computing Delay slot Computer architecture Computer hardware Computing
136	EN Case No COMP/M.2439 HITACHI / STMICROELECTRONIC S / SUPERH JV Add to Reading List Source URL: ec.europa.eu Language: English - Date: 2008-12-04 08:50:22 Instruction set architectures Microprocessors Acorn Computers Parallel computing Embedded microprocessors SuperH Reduced instruction set computing ARM Holdings SH4 Computer architecture Computing Computer hardware
137	Microsoft Word - ME-EST 2011 Regulations.doc Add to Reading List Source URL: nec.edu.in Language: English - Date: 2014-06-15 01:38:46 Computer hardware Embedded systems Microcontrollers TI MSP430 CPU design Scheduling Reduced instruction set computing Assembly language Central processing unit Computer architecture Electronic engineering
138	The Proposed Level-3 Trigger System for STAR C. Adler a , J. Berger a , M. Demello b , D. Flierl a , J. Landgraf c , J. S. Lange a; 1 , M. J. LeVine c , V. Lindenstruth d , A. Ljubicic,Jr. c , J. Nelson e , D. Roehrich f Add to Reading List Source URL: www.star.bnl.gov Language: English - Date: 2002-06-20 11:42:50 Instruction set architectures Computer memory Motherboard Intel i960 Microcontrollers Classes of computers DEC Alpha CPU cache Reduced instruction set computing Computer hardware Computer architecture Computing
139	Processor-Specific ELF Supplement for PA-RISC Including HP and HP-UX Extensions Version 1.43 October 6, 1997 This document is a supplement to the processor-independent definitions of ELF-32 and ELF-64. It Add to Reading List Source URL: refspecs.linuxbase.org Language: English - Date: 2013-05-29 14:41:04 Instruction set architectures Assembly languages Reduced instruction set computing Executable and Linkable Format PA-RISC Addition Addressing mode Relocation Ar Computing Computer architecture Software
140	Processor-Specific ELF Supplement for PA-RISC Including HP and HP-UX Extensions Version 1.43 October 6, 1997 This document is a supplement to the processor-independent definitions of ELF-32 and ELF-64. It Add to Reading List Source URL: refspecs.linux-foundation.org Language: English - Date: 2013-05-29 14:41:04 Instruction set architectures Assembly languages Reduced instruction set computing Executable and Linkable Format PA-RISC Addition Addressing mode Relocation Ar Computing Computer architecture Software

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